1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device that employs a MOS transistor, and in particular to a semiconductor integrated circuit device that is so configured as to prevent generation of a reverse current in a MOS transistor.
2. Description of the Prior Art
In a semiconductor integrated circuit device, there is often included a P-channel MOS transistor M1 having a supply voltage Vdd applied to a P-type diffusion layer and a backgate thereof as shown in FIG. 4A. As shown in FIG. 4B, this MOS transistor M1 is provided with P-type diffusion layers 11 and 12, an N-type diffusion layer 14 functioning as a backgate, and a gate formed on the surface of an N-type well layer 10 with an insulating film 13 laid in between. Here, the P-type diffusion layer 11, the N-type well layer 10, and the N-type diffusion layer 14, i.e., the backgate, together form a PN junction that functions as a parasitic diode Dx.
Thus, when the MOS transistor M1 is reversely biased, a reverse current flows from the P-type diffusion layer 11 through the parasitic diode Dx to the P-type diffusion layer 12 and to the N-type diffusion layer 14. To prevent this reverse current, as shown in FIG. 4C, in the path leading from the P-type diffusion layer 12 and backgate of the MOS transistor M1 to the supply voltage Vdd, there is often provided a diode Da having the supply voltage Vdd applied to the anode thereof. Inconveniently, however, this diode provided for protection against a reverse current causes a voltage loss.
There has conventionally been proposed an output stage circuit wherein a reverse current is prevented without causing a voltage loss as is caused by an anti-reverse-current diode as described above (Japanese Patent Application No. H10-341141). In the output stage circuit proposed in this publication, a switch is provided in the path leading from the source and backgate of a P-channel MOS transistor to the supply voltage so that, when a supply voltage monitoring circuit recognizes a drop in the supply voltage, the switch is turned off to thereby prevent a reverse current.
However, the supply voltage monitoring circuit provided for protection against a reverse current according to the Japanese Patent Application No. H10-341141 mentioned above is composed of inverters or NAND gates and thus, when it is operating normally, a P-channel MOS transistor that functions as the switch is kept on by receiving at the gate thereof a ground voltage from the supply voltage monitoring circuit. That is, while in use, the P-channel MOS transistor used as the switch keeps continuously receiving at the gate thereof the ground potential, and this makes the P-channel MOS transistor used as the switch susceptible to breakdown. To prevent breakdown, it is necessary to set the supply voltage Vdd to be lower than the withstand voltage, and this limits the application of such a configuration.